1. Field of the Invention
The present invention relates to data input/output of a sense amplifier in a semiconductor memory device.
2. Description of the Related Art
A NAND flash memory is an example of semiconductor memories. Demands for this NAND flash memory are abruptly increasing as applications in which large volumes of data such as still images and motion images are processed in mobile apparatuses and the like increase. The size of a memory cell of the NAND flash memory shrinks for each generation in order to increase the memory capacity.
When the memory cell size shrinks, the bit line pitch also shrinks. Accordingly, the size is determined with respect to the bit line pitch, and a sense amplifier formed in a page buffer also shrinks (see, e.g., Jpn. Pat. Appln. KOKAI Publication No. 2007-213806). Consequently, the data line drivability of the sense amplifier degrades, so it takes a long time to obtain the total amplitude of a data line.
When reading data from the sense amplifier, therefore, a differential amplifier placed in a peripheral region amplifies data read to a data line, and transfers the amplification result to a read data line.
In addition, precharge and equalization are performed to prepare for the next read. A precharger and equalizer for performing these operations are also formed in the peripheral circuit.
That is, the differential amplifier, precharger, and equalizer to be used in data read are formed in the peripheral circuit. Therefore, the data line is extended to the peripheral region and electrically connected to these circuits.
Since the differential amplifier, precharger, and equalizer are formed in the peripheral circuit, a temporal delay occurs before the effects of these circuits propagate to the data line. This prolongs the time required to read data from the sense amplifier.
The time required to read data from the sense amplifier accounts for a high ratio in the data input/output time. Accordingly, the increase in time required to read data from the sense amplifier is a serious problem for a high speed required of a memory cell.